The present invention relates to integrated circuit design, and more specifically, to pessimism reduction in cross-talk noise determination used in integrated circuit design.
The fabrication of an integrated circuit involves a number of stages from a logic design through physical synthesis. During the layout process of the physical synthesis phase, the effect of cross-talk noise (i.e., coupled noise) must be considered. Coupled noise is unwanted energy transferred to a net (i.e., the connection between two or more logic gates or other components, referred to as nodes) from one or more other nets. The affected net can be referred to as a victim net and the nets generating the coupled noise can be referred to as aggressor nets. Coupled noise is typically represented as a voltage signal and can affect timing and functionality of the victim net and corresponding nodes. For example, coupled noise on the victim net can increase charge time (i.e., time to reach a threshold charge that indicates arrival time of a signal) and, consequently, increase the delay at the receiver end of the victim net. As another example, coupled noise over a threshold level can cause a gate connected to the victim net to malfunction. While estimating and addressing coupled noise in the victim net are important to ultimately meeting timing and operational constraints, overestimating coupled noise, referred to as pessimism in the estimate, can lead to unnecessary overdesigning of the integrated circuit.